Pseudo random counter decoding

Jul 2010

I have a pseudo random counter that looks like below.
Briefly what it does is to generate a "random" number every time the system is clocked.
I say "random" and not random because the register values in the counter follows the same pattern every time, if you start from 0.

If the feedback to the first register is done correctly throe the three XNOR logical blocks, the next number that appears in the register will not be similar to any other you can generate. Meaning that if you have 12 bits, you get 2e12 different combination's. With one exception, the very last clock is not correct, so it has to be skipped.

So what you end up with using a counter like this is 4095 pseudo random numbers reaching from 0 to 4094 in binary.

What I want to do is to calculate how many clock cycles it took to reach any of the values that can be in the 12 bit register.

This can be done with a lookup table. Or with logical block working like a transform from the scrambled numbers to the binary order [00 0000 0000], [00 0000 0001], [00 0000 0010], .... [11 1111 1110], [11 1111 1111].

But as the pseudo random counter works beautifully with just three logical blocks, the three XNORs, isn't there a as beautiful way to transfor/decode it back? With a minimal amount of logical blocks and clock cycles.

Miniature example:
I want to find out how I can in the smallest way convert any component of series A into its corresponding component (component with same index) of series B.
A = [01 11 00 10]
B = [00 01 10 11]
And the answer would be how the logic decoder works in, A(x) applied to logic decoder = B(x). Where x is any of the series [0 1 2 3].

The background to this is that the pseudo random counter is realized in a silicon chip because it is so small compared to a binary counter. But immense amounts of data will then need to be decoded in a computer (over 1 TB/s), and that will not be possible. So if possible, a decoder could be implemented in the silicon chip to decode the pseudo random numbers before sent to a computer. So that 1 million pseudo random counters are converted using a few thousand decoders every millisecond and then sent to a computer (first being buffered in a RAM). But the decoder has to be small enough to fit the silicon space, meaning minimum amounts of logical blocks (transistors).

I would be very grateful if anyone who has experience in this could have a look and help me.